Circulating Current Suppression in Parallel Interleaved 2L VSIs Using Modified CM Offset Based Method During Inductors Mismatch Condition

Parallel interleaved two-level voltage source inverters (VSIs) could be analyzed as a single multilevel VSI and hence, significance reduction in the grid side current ripple achieved. However, parallel VSIs have major issue of circulating current. The is mainly composed two frequency components: high component low component. generated due to instantaneous difference common-mode (CM) voltages VSIs. While inductance value mismatch ac line inductors, also flows system. This needs controlled it saturate CM, coupled, or interphase inductors used for limiting In this article, an analysis carried out during condition. A CM offset signal proposed limit flow derived terms existing signals, hence any pulsewidth modulation technique implemented using method. Simulation experimental results show improvement modified offset.